The AV140 is part of ApisSys' range of High-Speed data conversion and signal processing solutions based on the VITA 46, VPX standard. The AV140 is SOSA aligned with RF signals on the backplane according to VITA 67.3 standard.
The AV140 is fully compliant with OpenVPX standard, accommodating various communication protocols such as PCIe, SRIO, and up to 40 Gbit Ethernet, as well as non OpenVPX adopted standard such as Aurora.
The AV140 combines four channel 12-bit 6 Gsps ADC and four channels 16-bit 12 Gsps DAC with ultra-high processing power delivered by Xilinx® Virtex® Ultrascale+™ FPGA, making it ideally suited for embedded signal processing applications such as Electronic Warfare, Wideband Radar Transmitter/Receivers or Wideband Communication applications.
The AV140 features an internal ultra-low jitter reference and one clock synthesizer and can be used with either external clock or external reference for higher flexibility.
The AV140 includes one Xilinx® Virtex® Ultrascale+™ VU13P FPGA for an impressive processing capability of more than 19 TMACs (Multiply Accumulate per second), two 1G64 DDR4-2666 SDRAM memory for data processing and one 2 Gb synchronous FLASH memory for multiple firmware storage. The AV140 can also be fitted with one Xilinx® Virtex® Ultrascale+™ VU9P FPGA.
The AV140 provides a UART and a USB 2.0 interfaces intended to be used for system monitoring and supervision.
The AV140 comes with complete software drivers for Windows and Linux. An FPGA Development Kit is provided including all necessary cores to build user FPGA application.
DESCRIPTION

12-BIT 6 GSPS ADCS

The AV140 Analog to Digital conversion is performed by two Analog Devices AD9082 Mixed Signal Front Ends (MxFE®) dual-channel 12-bit 6 Gsps ADC The AV140 provides four SMPM for analog inputs on the 14-port VITA 67.3 connector. Single ended input signals are AC coupled with a usable input bandwidth from 10 MHz to more than 8 GHz with (TBD) dBm input level.

16-BIT 12 GSPS DACS

The AV140 Digital to Analog conversion is performed by two Analog Devices AD9082 Mixed Signal Front Ends (MxFE®) dual-channel 16-bit 12 Gsps DAC. The AV140 provides four SMPM for analog outputs on a 14-port VITA 67.3 connector. Single ended output signals are AC coupled with a usable ouput bandwidth from 10 MHz to more than 8 GHz with (TBD) dBm output level (NRZ).

CLOCK

The AV140 provides one ultra-low jitter clock synthesizer locked on a 100 MHz internal reference. The AV140 supports a 10 to 500 MHz external reference input from a SMPM on the 14-port VITA 67.3 connector. A reference output is available on the VITA 67.3 connector. An external sampling clock input from 4 GHz to 12 GHz is supported from one SMPM on the 14-port VITA 67.3 connector.

CALIBRATION

A wideband signal generator plus internal loopback from the DAC output allow for stand-alone calibration of all ADC and DAC channels. External input and output calibration signals are supported on the 14-port VITA 67.3 connector.

FPGA

The AV140 is fitted with a Xilinx® Virtex® Ultrascale+™ VU9P or VU13P user programmable FPGA. Only few resources are used to control and communicate with external hardware such as DDR4 SDRAM and monitoring sub-system, leaving most of the logic and block RAM and all DSP resources available for customer processing. Dedicated to signal processing, the Xilinx Virtex Ultrascale+ VU13P FPGA includes 3,780 K logics cells, 94.5 Mbit of RAM blocs, 360 Mbit of Ultra RAM, 4 PCIe GEN3x16 interface blocs and 12,288 DSP48 slices for an impressive processing power of more than 19 TMACs. The FPGA is delivered in -2 speed grade.

MEMORIES

The AV140 includes two 512M64 (1G64) DDR4-2666 SDRAM memory banks and one 2 Gbit QSPI FLASH used to store multiple FPGA configuration files.

VPX INTERFACE

The AV140 features an OpenVPX VITA 65 compliant interface, SOSA aligned, with support for one Fat Pipe and one Ultra-Thin Pipe for Data Planes, one Ultra-Thin Pipe for Control Plane and two Fat Pipes for Expansion Plane on P1. The AV140 features one low phase noise clock generator able to synthesize the clock references for the FPGA GTYs from 60 MHz to 820 MHz, allowing support of all major protocols such as Aurora, 10 and 40GigE, PCIe Gen 1, 2 and 3, SATA, SRIO and 1Gbit Ethernet up to 28 Gbps.

MICROCONTROLLER

The AV140 features a 32-bit 80 MHz microcontroller used primarily for board monitoring and supervision. The microcontroller supports a USB 2.0 and a UART interfaces accessible on the front panel. The microcontroller firmware includes all necessary features for board monitoring and supervision.

FIRMWARE

The AV140 comes with a firmware package which includes VHDL cores allowing for control and communication with all AV140 hardware resources. A base design is provided which demonstrates the use of the AV140 and gives users a starting point for firmware development. The AV140 firmware package is supported on the Xilinx VIVADO® 2020.2 design suite.

SOFTWARE

The AV140 is delivered with software drivers for Windows 10 and Linux.

RUGGEDIZATION

The AV140 is delivered in air cooled and conduction cooled standard or rugged versions for use in severe environmental conditions. Standard VITA 47 supported ruggedization levels are EAC4, EAC6, ECC3 and ECC4.

ARCHITECTURE

SPECIFICATIONS

ANALOG INPUT/OUTPUT

Input coupling: AC
Full power bandwidth: > 8 GHz
Full scale : TBD dBm
Output Coupling: AC
Full power bandwith: > 8 GHz
Full scale : TBD dBm (NRZ)
Impedance: 50 Ohm
Connectors: SMPM on VITA 67.3

ANALOG-DIGITAL CONVERSION

Four channels, Fs ≤ 6 GHz
Resolution: 16 bit
Sampling performances @2.1GHz -1 dBFs
SNR: 54 dBFs
SFDR: 70 dBc
ENOB: 8.6 bits

DIGITAL-ANALOG CONVERSION

Four channels, Fs ≤ 12 GHz
Resolution: 16 bit
Sampling performances @2.1GHz -7 dBFs
SFDR: 68 dBc
NSD: -160 dBc/Hz

CLOCK

Internal:
One ultra-low jitter clock synthesizer
4 GHz to 12 GHz low jitter clock
External Input Clock:
Frequency: 4 GHz to 12 GHz
Input level: 10 dBm recommended
Connector: SMPM 50 Ohm on VITA 67.3
External reference:
Frequency: 10 MHz to 500 MHz
Connector: SMPM 50 Ohm on VITA 67.3

CALIBRATION

One low jitter signal generator
Frequency: 1 Ghz to 4.5 GHz
External Calibration Input and Output
Connectors: SMPM 50 Ohms on VITA 67.3

FPGA

FPGA: Xilinx Virtex Ultrascale+
XCVU13P-2FHGB2104I
XCVU9P-2FLBG2104I

MEMORY

Two banks 512M64 DDR4 SDRAM, 1333 MHz clock
Support up to two banks 1G64 DDR4 SDRAM
One 2 Gbit QSPI FLASH memory

VPX INTERFACE

P1:
Data plane: one fat pipe and one ultra-thin pipe
Control plane: one ultra-thin pipe
Expansion plane: two fat pipes
P2:
VITA 67.3 14-port

SOFTWARE SUPPORT

Software Drivers:
Windows 10 64-bits
Linux 64-bits
Application example: Windows and Linux

FIRMWARE SUPPORT

VHDL cores for all hardware resources
Base design
Supported by Xilinx VIVADO 2020.2

RUGGEDIZATION

As per VITA 47:
Air cooled : EAC4 and EAC6
Conduction cooled : ECC4

POWER DISSIPATION

+12V: 11.9 A max (143W)
+3.3VAUX: 0.6 A max (2W)

WEIGHT

Air cooled : 550g
Conduction cooled : 650g